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Through Silicon Insulator (TSI™)

TSI™ White Paper

Silex Standard Packaging Process Technologies

Silex Standard Packaging Process Technologies White Paper

Advanced MEMS Process Technology

SILEX MICROSYSTEMS strategy recognizes that MEMS foundries will lead technology development when it comes to the evolution of advanced processing capability. Silex team of MEMS experts provides a solid foundation for technological innovation and enables the development of proprietary process technologies for the most advanced MEMS solutions. Innovation is a core value at Silex; from the set-up of process to volume manufacturing.

Having used CMOS foundries as benchmark, we have followed the trend of the IC industry and are leveraging an extensive processing expertise when developing advanced process IP to complement the MEMS foundry manufacturing offer.

It is generally acknowledged that main hurdles in the commercialization of MEMS are related to packaging and interconnect of the MEMS die. Silex has worked on developing process solutions that will solve the inherent problems of packaging and interconnect since the first year of operation.

Metal Via Wafer Level Packaging (Met-Cap™)

Silex has recently completed development of a through full wafer thickness metal via capping technology (Met-Cap™) where the metal-via is integrated in a cap wafer that may also contain a cavity and possibly other more advanced functionality (integrated passive devices – IPD’s). By offering a well characterized standard capping process platform we reduce the need for unique process development to overcome limitations posed by the specific design of a device wafer. Utilizing a standardized process platform approach, there is a significant reduction in development cost, risk and time to market. Silex 6” and 8” fabs are equipped with the latest generation equipment and process technology to create cost efficient and high yielding 3D integration technologies.

Silex Met-Cap™ technology utilizes licensed metal via technology from AAC Microtec (XiVIA®) to solve the inherent reliability issues relating to thermal mismatch of metals and standard wafer substrates, enabling thick wafer metal vias. Silex Cu based Met-Cap™ solution exhibits a total yield <25 mOhm per via in 300 µm thick wafer substrates. With wafer level capping being one of the strongest trends in device development today, Silex approach to host a robust 3D interconnect functionality in the required cap wafer enables a fast adoption into a wide range of applications already on the market today.

Through Silicon Via (Sil-Via®)

Silex TSI™ technology consists of a through wafer trench created by DRIE that is filled with an isolating dielectric. If the TSI™ technology is applied to a highly doped Si wafer, a closed vertical trench around a “plug” of Si will constitute an isolated electrical connection through the wafer, or a through silicon via – TSV.

Through Silicon Via Technology (Sil-Via®)

Silex is marketing this proprietary through silicon wafer interconnect process under the brand name (Sil-Via®). Integration of the Sil-Via® into MEMS systems enables significantly reduced form factor and true wafer level packaging solutions. The technology can also be incorporated into the handle side of an SOI wafer, allowing the combination of a highly doped handle wafer and a low doped device layer.
This approach of isolating a conductive area through the wafer is the inverse of the more common approach of making a hole and filling it with something conductive. In contrast to most announced through silicon via processes, Silex (Sil-Via®) technology has a proven history of volume production supply into a wide range of MEMS applications, including the cellular handset market.

Zero-Crosstalk™ Feature

Many MEMS products comprise a combination of analogue and digital signal processing. Typical sensor readout for MEMS sensors is of analogue type but also incorporate digital signal processing, taking place in an ASIC, flip chip mounted to the MEMS die. In many cases, the system will be sensitive to signal contamination between the analogue and digital side of the system.

Zero-Crosstalk™ Feature

Silex Through Silicon Insulator (TSI™) technology is applied to create vertical walls, separating certain regions of an IC chip or MEMS die in order to reduce signal contamination and crosstalk. Even pure IC’s with mixed signal processing will benefit from the technology as the isolating walls can be incorporated within the die layout. Silex is offering this feature of the Through Silicon Insulator technology under the brand name Zero-Crosstalk™.

Zero-Crosstalk™ DRIE Process

The Zero-Crosstalk™ feature originated in a design element for a low pitch through silicon via. A via layout with pitch in the order of 50 um between each interconnect requires each adjacent TSV to share the same isolating trench. In essence the element became a chain of isolated through silicon interconnects. The chain could then be laid out in the die to constitute a closed loop, confining a closed area within the loop that is electrically isolated from the rest of the die. No additional alterations were necessary to achieve the add-on feature and both the TSV and the Zero Crosstalk feature are formed at the same time providing a novel solution for manufacturers struggling to deal with the noise between digital and analogue processing that can occur and have a negative impact on the completed device.

Metal Via Process (Met-Via®)

In order to support requirements from RF MEMS foundry customers, Silex has over the past years worked on developing a metal-via process suitable to meet the stringent requirements of sub 50 mOhm total through wafer via resistance in combination with tough demands on hermeticity. Silex new 8” line is boasting a world leading equipment installation base that combined with Silex processing expertise offers the best metal via processing capability that is available today.

Wafer Level - Micro Scale Packaging (WL-MSP™)

Traditional packaging of electronic components is based on low temperature or high temperature co-fired ceramics (LTCC or HTCC). With the trend of ever decreasing component form factors, advanced small scale packaging may in the foreseeable future require other materials than ceramics to achieve the accuracy and reduction in footprint requested by the market. To some extent the limit may already have been reached for some ceramic based technologies as the existing manufacturing methods have difficulties achieving the small pitch for electrical feedthroughs (<100 ìm) and tight tolerances required when moving closer to “micro scale”. In that respect, silicon stands out as a very good candidate with its long term reliability and high precision micromachining capabilities. In this respect, Silex Sil-Via® technology and MEMS processing technology can be applied to realize customized silicon based Wafer Level Packaging (WLP) solutions.

Wafer Level - Micro Scale Packaging (WL-MSP™)

Functional Capping™ Process

As an extension of Silex expertise on the metal via technology and wafer bonding; Silex offers its customer a proprietary packaging solution. Silex novel capping approach comprises a proprietary SOI device layer transfer process in combination with a CMOS compatible hermetic wafer bond seal that also enables the easy integration RF passives, sealed cavities, Zero-Crosstalk™ and coaxial feedthroughs in additional to the Met-Via® through wafer via interconnect.

Standard Process Approach

Silex is committed to setting new standards in the MEMS industry by leading the task to standardize the MEMS foundry process offer. In essence, this means that Silex strives towards creating robust and well characterized process blocks and modules that are compatible and well suited to be assembled together in the realiziation of our customers’ designs.

In order to achieve such high ambitions, Silex is leveraging the experience and expertise from manufacturing well over 100 MEMS products to date.