Sil-Via, TSI & Advanced Features

Advanced MEMS Process Technology

As the world’s foremost pure-play MEMS foundry, Silex is on the leading edge of technology development for advanced processing capability. Our experienced MEMS experts provide a solid basis for technological innovation and allow us to develop proprietary process technologies for the most advanced MEMS solutions. Innovation is a core value at Silex—from set-up to volume manufacturing. Using the best CMOS foundries as a benchmark, Silex leverages our extensive expertise when developing advanced process IP to complement our MEMS foundry manufacturing capabilities. A major hurdle in the commercialization of MEMS is the packaging and interconnect of the MEMS die. Since day one, it has been a Silex priority to develop process solutions that can solve the inherent problems of packaging and interconnect, thereby smoothing the way for MEMS commercialization.

Met-Via™ Through-Silicon Vias

Silex Met-Via TSV Silex offers a full-wafer thickness all metal TSV which can be used for interposers, MEMS substrates, and Through-Mold Vias (TMVs). This high reliability, cost effective approach to TSVs at 300 to 400um wafer thickness means that advanced 2.5D and 3D packaging solutions can be realized without the need for thin wafer handling or special bonding/debonding procedures.

Metal Via Wafer Level Packaging (Met-Cap™)

Silex recently completed development of a through full wafer thickness metal via capping technology (Met-Cap™) in which the metal-via is integrated in a cap wafer that may also contain a cavity and possibly other more advanced functionality, such as integrated passive devices. By offering a well-characterized standard capping process platform, we reduce the need for unique process development to overcome limitations posed by the specific design of a device wafer. Utilizing a standardized process platform approach, there is a significant reduction in development cost, risk and time to market.

Silex Met-Cap™ and Met-Via™ technologies solve the inherent reliability issues related to thermal mismatch of metals and standard wafer substrates, enabling thick wafer metal vias. The Silex Cu based Met-Cap™ solution exhibits a total yield <25 mOhm per via in 300 µm thick wafer substrates. With wafer level capping being one of the strongest trends in device development today, our unique approach of hosting a robust 3D interconnect functionality in the required cap wafer enables fast adoption into a wide range of applications on the market today.

Sil-Via® TSVs: the most widely recognized all-silicon through-silicon via

Silex is widely recognized for Sil-Via® TSVs, the all-silicon through-silicon via which has been in continuous production since 2006, and used on over 100 MEMS devices.  The Sil-Via® TSV was developed to address reliability challenges of metal TSVs which existed in the mid 2000′s by creating a TSV formed out of single-crystal silicon and filled with an isolating dielectric.

Through Silicon Via Technology (Sil-Via® TSV)

Integration of the Silex Sil-Via® TSV into MEMS systems enables significantly reduced form factors and true wafer level packaging solutions. The technology can also be incorporated into the handle side of an SOI wafer, allowing the combination of a highly doped handle wafer and a low doped device layer.  This approach of isolating a conductive area through the wafer is the inverse of the more common approach of making a hole and filling it with something conductive. In contrast to most commonly-used through silicon via processes, the Silex Sil-Via® TSV has a proven history of volume production in a wide range of MEMS applications, including the cellular handset market.

Zero-Crosstalk™ Feature

Many MEMS products consist of a combination of analog and digital signal processing. Typical readouts for MEMS sensors are analog + DSP mixed signal ASICs, flip chip mounted to the MEMS die. In many cases, the system will be sensitive to signal contamination between the analog and digital side of the system.

Zero-Crosstalk™ Feature

To reduce signal contamination and crosstalk, Silex’s Through Silicon Insulator (TSI™) technology creates vertical walls, separating certain regions of an IC chip or MEMS die. Even pure IC’s with mixed signal processing will benefit from this technology as the isolating walls can be incorporated within the die layout. Silex calls this feature of the Through Silicon Insulator technology Zero-Crosstalk™.

 

Zero-Crosstalk™ DRIE Process

The Zero-Crosstalk™ feature developed as an offshoot from low pitch TSV development. A via layout with pitch in the order of 50 um between each interconnect requires each adjacent TSV to share the same isolating trench. In essence, the element became a chain of isolated through silicon interconnects. The chain could then be laid out in the die to constitute a closed loop, confining a closed area within the loop that is electrically isolated from the rest of the die. No additional processing steps are needed to achieve the add-on feature and both the TSV and the Zero Crosstalk feature are formed at the same time, providing a novel solution for manufacturers struggling to deal with the noise between digital and analog processing that can have a negative impact on the completed device.

Wafer Level – Micro Scale Packaging (WL-MSP™)

Traditional packaging of electronic components is based on low temperature or high temperature co-fired ceramics (LTCC or HTCC). With the trend of ever decreasing component form factors, advanced small-scale packaging may in the foreseeable future require other materials than ceramics to achieve the accuracy and reduction in footprint required by the market. To some extent, the limit may already have been reached for some ceramic based technologies as the existing manufacturing methods have difficulties achieving the small pitch for electrical feedthroughs (<100 μm) and tight tolerances required when moving closer to “micro scale”. In that respect, silicon stands out as a very good candidate with its long-term reliability and high precision micromachining capabilities. Silex’s Sil-Via® technology and MEMS processing technology can be applied to achieve customized silicon based Wafer Level Packaging (WLP) solutions.

Wafer Level – Micro Scale Packaging (WL-MSP™)

 

Functional Capping™ Process

Functional Capping™ Process

As an extension of our expertise on the metal via technology and wafer bonding, Silex offers its customer a proprietary packaging solution. Our novel capping approach consists of a proprietary SOI device layer transfer process in combination with a CMOS compatible hermetic wafer bond seal that enables the easy integration RF passives, sealed cavities, Zero-Crosstalk™ and coaxial feedthroughs, in addition to the Met-Via® TSV through wafer via interconnect.